//==============================================
// CSU18M68 Special Register Address Definition
// Date:2020-03-25
// Version: V1.0.0 
//==============================================

#ifndef  _CSU18M68_H
#define  _CSU18M68_H 1


#define DISABLE                  0
#define ENABLE                   1

//Data Memory Organization 00h-08h
extern volatile unsigned char IND0             @ 0x00;     //{  }
extern volatile unsigned char IND1             @ 0x01;     //{  }
extern volatile unsigned char FSR0             @ 0x02;     //{  }
extern volatile unsigned char FSR1             @ 0x03;     //{  }
extern volatile unsigned char STATUS           @ 0x04;     //{ 0, 0, 0, PD, TO, DC, C, Z }
extern volatile unsigned char WORK             @ 0x05;     //{  }
extern volatile unsigned char INTF             @ 0x06;     //{ 0, 0, TM1IF, TM0IF, 0, ADIF, E1IF, E0IF }
extern volatile unsigned char INTE             @ 0x07;     //{ GIE, 0, TM1IE, TM0IE, 0, ADIE, E1IE, E0IE }
extern volatile unsigned char BSR              @ 0x08;     //{ IRP0, IRP1, 0, 0, 0, 0, PAGE1, PAGE0 }

//Peripheral special registers 09h-7Fh
extern volatile unsigned char MCK              @ 0x09;     //{ 0, M3_CK, 0, 0, 0, WDT_CLK_EN, 0, 0 }
extern volatile unsigned char EADRH            @ 0x0A;     //{ PROG_BUSY, READ_CHECK, PARH[5:0] }
extern volatile unsigned char EADRL            @ 0x0B;     //{ PARL[7:0] }
extern volatile unsigned char EDAT             @ 0x0C;     //{ EDAT[7:0] }
extern volatile unsigned char EOPEN            @ 0x0D;     //{ EOPEN[7:0] }
extern volatile unsigned char WDTCON           @ 0x0E;     //{ WDTEN, ROOT_EN, 0, I2C_DIV[1:0], WDTS[2:0] }
extern volatile unsigned char WDTIN            @ 0x0F;     //{ WDTIN[7:0] }
extern volatile unsigned char ADOH             @ 0x11;     //{ ADO[15:8] }
extern volatile unsigned char ROOT             @ 0x13;     //{ ROOT[-1:-1] }
extern volatile unsigned char RSTSR            @ 0x14;     //{ 0, 0, 0, 0, LVDF, EMCF, ILOPF, 0 }
extern volatile unsigned char ADCFG            @ 0x16;     //{ ADSC, 0, 0, S_GAIN[1:0], 0, CHOPM[1:0] }
extern volatile unsigned char ANACFG           @ 0x17;     //{ LDOEN, LDOS[1:0], BGR_ENB, BGID, SINL[1:0], ADEN }
extern volatile unsigned char LVDCON           @ 0x1B;     //{ LVDEN, 0, AIENB1, SILB[2:0], LBOUT, LB_RST_CON }
extern volatile unsigned char ADOL             @ 0x1C;     //{ ADO[7:0] }
extern volatile unsigned char PT1              @ 0x1D;     //{ 0, 0, PT1[5:0] }
extern volatile unsigned char PT1EN            @ 0x1E;     //{ 0, 0, PT1EN[5:0] }
extern volatile unsigned char PT1PU            @ 0x1F;     //{ 0, 0, 0, 0, 0, 0, PT1UP[1:0] }
extern volatile unsigned char INPUT            @ 0x2C;     //{ PT15_VDD, PT14_VDD, I2C_VDD, PT11_VDD, PT10_VDD, I2C_FLT, PT11_OD, PT10_OD }
extern volatile unsigned char PTCON            @ 0x2D;     //{ 0, 0, 0, 0, E1M[1:0], E0M[1:0] }
extern volatile unsigned char PTINT0           @ 0x2E;     //{ 0, 0, 0, 0, 0, PTW0[2:0] }
extern volatile unsigned char PTINT1           @ 0x2F;     //{ 0, 0, 0, 0, 0, PTW1[2:0] }
extern volatile unsigned char TM0CON           @ 0x34;     //{ T0EN, T0RATE[2:0], 0, T0RSTB, 0, T0SEL }
extern volatile unsigned char TM0IN            @ 0x35;     //{ TM0IN[7:0] }
extern volatile unsigned char TM0CNT           @ 0x36;     //{ TM0CNT[7:0] }
extern volatile unsigned char TM1CON           @ 0x37;     //{ T1EN, T1RATE[2:0], 0, T1RSTB, 0, T1SEL }
extern volatile unsigned char TM1IN            @ 0x38;     //{ TM1IN[7:0] }
extern volatile unsigned char TM1CNT           @ 0x39;     //{ TM1CNT[7:0] }
extern volatile unsigned char INTF3            @ 0x5A;     //{ I2C_TIF, I2C_RIF, 0, 0, 0, I2C_STIF, 0, 0 }
extern volatile unsigned char INTE3            @ 0x5B;     //{ I2C_TIE, I2C_RIE, 0, 0, 0, I2C_STIE, 0, 0 }
extern volatile unsigned char I2CCON           @ 0x68;     //{ I2C_EN, AWK_EN, CST_EN, ACK_EN, I2CSTUS[3:0] }
extern volatile unsigned char I2CDAT           @ 0x69;     //{ I2CDAT[7:0] }
extern volatile unsigned char I2CISR           @ 0x6A;     //{ 0, 0, 0, 0, 0, 0, 0, TXE }
extern volatile unsigned char ADCON            @ 0x6B;     //{ VS0_OEN, VS_LIMIT, AINOUT[1:0], 0, 0, ADM[1:0] }
extern volatile unsigned char WDT_TRIM         @ 0x6D;     //{ TMOD[1:0], 0, 0, WDT_TRIM[3:0] }
extern volatile unsigned char ICK_TRIM         @ 0x6E;     //{ ICK_TRIM[7:0] }
extern volatile unsigned char VS_TRIM          @ 0x6F;     //{ SIM_RST, LVD_TRIM[2:0], VS_TRIM[3:0] }
extern volatile unsigned char METCH            @ 0x7E;     //{ METCH[3:0], EVPP_EN, 0, 0, 0 }
extern volatile unsigned char I2CADR           @ 0x7F;     //{ I2CADR[6:0] }

//-------------------------------------------------------
//  STATUS register bit map
//-------------------------------------------------------
extern volatile sbit Z                         @ 0x04*8+0;
extern volatile sbit C                         @ 0x04*8+1;
extern volatile sbit DC                        @ 0x04*8+2;
extern volatile sbit TO                        @ 0x04*8+3;
extern volatile sbit PD                        @ 0x04*8+4;

//-------------------------------------------------------
//  INTF register bit map
//-------------------------------------------------------
extern volatile sbit E0IF                      @ 0x06*8+0;
extern volatile sbit E1IF                      @ 0x06*8+1;
extern volatile sbit ADIF                      @ 0x06*8+2;
extern volatile sbit TM0IF                     @ 0x06*8+4;
extern volatile sbit TM1IF                     @ 0x06*8+5;

//-------------------------------------------------------
//  INTE register bit map
//-------------------------------------------------------
extern volatile sbit E0IE                      @ 0x07*8+0;
extern volatile sbit E1IE                      @ 0x07*8+1;
extern volatile sbit ADIE                      @ 0x07*8+2;
extern volatile sbit TM0IE                     @ 0x07*8+4;
extern volatile sbit TM1IE                     @ 0x07*8+5;
extern volatile sbit GIE                       @ 0x07*8+7;

//-------------------------------------------------------
//  BSR register bit map
//-------------------------------------------------------
extern volatile sbit PAGE0                     @ 0x08*8+0;
extern volatile sbit PAGE1                     @ 0x08*8+1;
extern volatile sbit IRP1                      @ 0x08*8+6;
extern volatile sbit IRP0                      @ 0x08*8+7;

//-------------------------------------------------------
//  MCK register bit map
//-------------------------------------------------------
extern volatile sbit WDT_CLK_EN                @ 0x09*8+2;
extern volatile sbit M3_CK                     @ 0x09*8+6;

//-------------------------------------------------------
//  EADRH register bit map
//-------------------------------------------------------
extern volatile sbit PARH_0                    @ 0x0A*8+0;
extern volatile sbit PARH_1                    @ 0x0A*8+1;
extern volatile sbit PARH_2                    @ 0x0A*8+2;
extern volatile sbit PARH_3                    @ 0x0A*8+3;
extern volatile sbit PARH_4                    @ 0x0A*8+4;
extern volatile sbit PARH_5                    @ 0x0A*8+5;
extern volatile sbit READ_CHECK                @ 0x0A*8+6;
extern volatile sbit PROG_BUSY                 @ 0x0A*8+7;

//-------------------------------------------------------
//  EADRL register bit map
//-------------------------------------------------------
extern volatile sbit PARL_0                    @ 0x0B*8+0;
extern volatile sbit PARL_1                    @ 0x0B*8+1;
extern volatile sbit PARL_2                    @ 0x0B*8+2;
extern volatile sbit PARL_3                    @ 0x0B*8+3;
extern volatile sbit PARL_4                    @ 0x0B*8+4;
extern volatile sbit PARL_5                    @ 0x0B*8+5;
extern volatile sbit PARL_6                    @ 0x0B*8+6;
extern volatile sbit PARL_7                    @ 0x0B*8+7;

//-------------------------------------------------------
//  EDAT register bit map
//-------------------------------------------------------
extern volatile sbit EDAT_0                    @ 0x0C*8+0;
extern volatile sbit EDAT_1                    @ 0x0C*8+1;
extern volatile sbit EDAT_2                    @ 0x0C*8+2;
extern volatile sbit EDAT_3                    @ 0x0C*8+3;
extern volatile sbit EDAT_4                    @ 0x0C*8+4;
extern volatile sbit EDAT_5                    @ 0x0C*8+5;
extern volatile sbit EDAT_6                    @ 0x0C*8+6;
extern volatile sbit EDAT_7                    @ 0x0C*8+7;

//-------------------------------------------------------
//  EOPEN register bit map
//-------------------------------------------------------
extern volatile sbit EOPEN_0                   @ 0x0D*8+0;
extern volatile sbit EOPEN_1                   @ 0x0D*8+1;
extern volatile sbit EOPEN_2                   @ 0x0D*8+2;
extern volatile sbit EOPEN_3                   @ 0x0D*8+3;
extern volatile sbit EOPEN_4                   @ 0x0D*8+4;
extern volatile sbit EOPEN_5                   @ 0x0D*8+5;
extern volatile sbit EOPEN_6                   @ 0x0D*8+6;
extern volatile sbit EOPEN_7                   @ 0x0D*8+7;

//-------------------------------------------------------
//  WDTCON register bit map
//-------------------------------------------------------
extern volatile sbit WDTS_0                    @ 0x0E*8+0;
extern volatile sbit WDTS_1                    @ 0x0E*8+1;
extern volatile sbit WDTS_2                    @ 0x0E*8+2;
extern volatile sbit I2C_DIV_0                 @ 0x0E*8+3;
extern volatile sbit I2C_DIV_1                 @ 0x0E*8+4;
extern volatile sbit ROOT_EN                   @ 0x0E*8+6;
extern volatile sbit WDTEN                     @ 0x0E*8+7;

//-------------------------------------------------------
//  WDTIN register bit map
//-------------------------------------------------------
extern volatile sbit WDTIN_0                   @ 0x0F*8+0;
extern volatile sbit WDTIN_1                   @ 0x0F*8+1;
extern volatile sbit WDTIN_2                   @ 0x0F*8+2;
extern volatile sbit WDTIN_3                   @ 0x0F*8+3;
extern volatile sbit WDTIN_4                   @ 0x0F*8+4;
extern volatile sbit WDTIN_5                   @ 0x0F*8+5;
extern volatile sbit WDTIN_6                   @ 0x0F*8+6;
extern volatile sbit WDTIN_7                   @ 0x0F*8+7;

//-------------------------------------------------------
//  ADOH register bit map
//-------------------------------------------------------
extern volatile sbit ADO_8                     @ 0x11*8+0;
extern volatile sbit ADO_9                     @ 0x11*8+1;
extern volatile sbit ADO_10                    @ 0x11*8+2;
extern volatile sbit ADO_11                    @ 0x11*8+3;
extern volatile sbit ADO_12                    @ 0x11*8+4;
extern volatile sbit ADO_13                    @ 0x11*8+5;
extern volatile sbit ADO_14                    @ 0x11*8+6;
extern volatile sbit ADO_15                    @ 0x11*8+7;

//-------------------------------------------------------
//  ROOT register bit map
//-------------------------------------------------------
extern volatile sbit ROOT_0                    @ 0x13*8+0;
extern volatile sbit ROOT_1                    @ 0x13*8+1;
extern volatile sbit ROOT_2                    @ 0x13*8+2;
extern volatile sbit ROOT_3                    @ 0x13*8+3;
extern volatile sbit ROOT_4                    @ 0x13*8+4;
extern volatile sbit ROOT_5                    @ 0x13*8+5;
extern volatile sbit ROOT_6                    @ 0x13*8+6;
extern volatile sbit ROOT_7                    @ 0x13*8+7;

//-------------------------------------------------------
//  RSTSR register bit map
//-------------------------------------------------------
extern volatile sbit ILOPF                     @ 0x14*8+1;
extern volatile sbit EMCF                      @ 0x14*8+2;
extern volatile sbit LVDF                      @ 0x14*8+3;

//-------------------------------------------------------
//  ADCFG register bit map
//-------------------------------------------------------
extern volatile sbit CHOPM_0                   @ 0x16*8+0;
extern volatile sbit CHOPM_1                   @ 0x16*8+1;
extern volatile sbit S_GAIN_0                  @ 0x16*8+3;
extern volatile sbit S_GAIN_1                  @ 0x16*8+4;
extern volatile sbit ADSC                      @ 0x16*8+7;

//-------------------------------------------------------
//  ANACFG register bit map
//-------------------------------------------------------
extern volatile sbit ADEN                      @ 0x17*8+0;
extern volatile sbit SINL_0                    @ 0x17*8+1;
extern volatile sbit SINL_1                    @ 0x17*8+2;
extern volatile sbit BGID                      @ 0x17*8+3;
extern volatile sbit BGR_ENB                   @ 0x17*8+4;
extern volatile sbit LDOS_0                    @ 0x17*8+5;
extern volatile sbit LDOS_1                    @ 0x17*8+6;
extern volatile sbit LDOEN                     @ 0x17*8+7;

//-------------------------------------------------------
//  LVDCON register bit map
//-------------------------------------------------------
extern volatile sbit LB_RST_CON                @ 0x1B*8+0;
extern volatile sbit LBOUT                     @ 0x1B*8+1;
extern volatile sbit SILB_0                    @ 0x1B*8+2;
extern volatile sbit SILB_1                    @ 0x1B*8+3;
extern volatile sbit SILB_2                    @ 0x1B*8+4;
extern volatile sbit AIENB1                    @ 0x1B*8+5;
extern volatile sbit LVDEN                     @ 0x1B*8+7;

//-------------------------------------------------------
//  ADOL register bit map
//-------------------------------------------------------
extern volatile sbit ADO_0                     @ 0x1C*8+0;
extern volatile sbit ADO_1                     @ 0x1C*8+1;
extern volatile sbit ADO_2                     @ 0x1C*8+2;
extern volatile sbit ADO_3                     @ 0x1C*8+3;
extern volatile sbit ADO_4                     @ 0x1C*8+4;
extern volatile sbit ADO_5                     @ 0x1C*8+5;
extern volatile sbit ADO_6                     @ 0x1C*8+6;
extern volatile sbit ADO_7                     @ 0x1C*8+7;

//-------------------------------------------------------
//  PT1 register bit map
//-------------------------------------------------------
extern volatile sbit PT1_0                     @ 0x1D*8+0;
extern volatile sbit PT1_1                     @ 0x1D*8+1;
extern volatile sbit PT1_2                     @ 0x1D*8+2;
extern volatile sbit PT1_3                     @ 0x1D*8+3;
extern volatile sbit PT1_4                     @ 0x1D*8+4;
extern volatile sbit PT1_5                     @ 0x1D*8+5;

//-------------------------------------------------------
//  PT1EN register bit map
//-------------------------------------------------------
extern volatile sbit PT1EN_0                   @ 0x1E*8+0;
extern volatile sbit PT1EN_1                   @ 0x1E*8+1;
extern volatile sbit PT1EN_2                   @ 0x1E*8+2;
extern volatile sbit PT1EN_3                   @ 0x1E*8+3;
extern volatile sbit PT1EN_4                   @ 0x1E*8+4;
extern volatile sbit PT1EN_5                   @ 0x1E*8+5;

//-------------------------------------------------------
//  PT1PU register bit map
//-------------------------------------------------------
extern volatile sbit PT1UP_0                   @ 0x1F*8+0;
extern volatile sbit PT1UP_1                   @ 0x1F*8+1;

//-------------------------------------------------------
//  INPUT register bit map
//-------------------------------------------------------
extern volatile sbit PT10_OD                   @ 0x2C*8+0;
extern volatile sbit PT11_OD                   @ 0x2C*8+1;
extern volatile sbit I2C_FLT                   @ 0x2C*8+2;
extern volatile sbit PT10_VDD                  @ 0x2C*8+3;
extern volatile sbit PT11_VDD                  @ 0x2C*8+4;
extern volatile sbit I2C_VDD                   @ 0x2C*8+5;
extern volatile sbit PT14_VDD                  @ 0x2C*8+6;
extern volatile sbit PT15_VDD                  @ 0x2C*8+7;

//-------------------------------------------------------
//  PTCON register bit map
//-------------------------------------------------------
extern volatile sbit E0M_0                     @ 0x2D*8+0;
extern volatile sbit E0M_1                     @ 0x2D*8+1;
extern volatile sbit E1M_0                     @ 0x2D*8+2;
extern volatile sbit E1M_1                     @ 0x2D*8+3;

//-------------------------------------------------------
//  PTINT0 register bit map
//-------------------------------------------------------
extern volatile sbit PTW0_0                    @ 0x2E*8+0;
extern volatile sbit PTW0_1                    @ 0x2E*8+1;
extern volatile sbit PTW0_2                    @ 0x2E*8+2;

//-------------------------------------------------------
//  PTINT1 register bit map
//-------------------------------------------------------
extern volatile sbit PTW1_0                    @ 0x2F*8+0;
extern volatile sbit PTW1_1                    @ 0x2F*8+1;
extern volatile sbit PTW1_2                    @ 0x2F*8+2;

//-------------------------------------------------------
//  TM0CON register bit map
//-------------------------------------------------------
extern volatile sbit T0SEL                     @ 0x34*8+0;
extern volatile sbit T0RSTB                    @ 0x34*8+2;
extern volatile sbit T0RATE_0                  @ 0x34*8+4;
extern volatile sbit T0RATE_1                  @ 0x34*8+5;
extern volatile sbit T0RATE_2                  @ 0x34*8+6;
extern volatile sbit T0EN                      @ 0x34*8+7;

//-------------------------------------------------------
//  TM0IN register bit map
//-------------------------------------------------------
extern volatile sbit TM0IN_0                   @ 0x35*8+0;
extern volatile sbit TM0IN_1                   @ 0x35*8+1;
extern volatile sbit TM0IN_2                   @ 0x35*8+2;
extern volatile sbit TM0IN_3                   @ 0x35*8+3;
extern volatile sbit TM0IN_4                   @ 0x35*8+4;
extern volatile sbit TM0IN_5                   @ 0x35*8+5;
extern volatile sbit TM0IN_6                   @ 0x35*8+6;
extern volatile sbit TM0IN_7                   @ 0x35*8+7;

//-------------------------------------------------------
//  TM0CNT register bit map
//-------------------------------------------------------
extern volatile sbit TM0CNT_0                  @ 0x36*8+0;
extern volatile sbit TM0CNT_1                  @ 0x36*8+1;
extern volatile sbit TM0CNT_2                  @ 0x36*8+2;
extern volatile sbit TM0CNT_3                  @ 0x36*8+3;
extern volatile sbit TM0CNT_4                  @ 0x36*8+4;
extern volatile sbit TM0CNT_5                  @ 0x36*8+5;
extern volatile sbit TM0CNT_6                  @ 0x36*8+6;
extern volatile sbit TM0CNT_7                  @ 0x36*8+7;

//-------------------------------------------------------
//  TM1CON register bit map
//-------------------------------------------------------
extern volatile sbit T1SEL                     @ 0x37*8+0;
extern volatile sbit T1RSTB                    @ 0x37*8+2;
extern volatile sbit T1RATE_0                  @ 0x37*8+4;
extern volatile sbit T1RATE_1                  @ 0x37*8+5;
extern volatile sbit T1RATE_2                  @ 0x37*8+6;
extern volatile sbit T1EN                      @ 0x37*8+7;

//-------------------------------------------------------
//  TM1IN register bit map
//-------------------------------------------------------
extern volatile sbit TM1IN_0                   @ 0x38*8+0;
extern volatile sbit TM1IN_1                   @ 0x38*8+1;
extern volatile sbit TM1IN_2                   @ 0x38*8+2;
extern volatile sbit TM1IN_3                   @ 0x38*8+3;
extern volatile sbit TM1IN_4                   @ 0x38*8+4;
extern volatile sbit TM1IN_5                   @ 0x38*8+5;
extern volatile sbit TM1IN_6                   @ 0x38*8+6;
extern volatile sbit TM1IN_7                   @ 0x38*8+7;

//-------------------------------------------------------
//  TM1CNT register bit map
//-------------------------------------------------------
extern volatile sbit TM1CNT_0                  @ 0x39*8+0;
extern volatile sbit TM1CNT_1                  @ 0x39*8+1;
extern volatile sbit TM1CNT_2                  @ 0x39*8+2;
extern volatile sbit TM1CNT_3                  @ 0x39*8+3;
extern volatile sbit TM1CNT_4                  @ 0x39*8+4;
extern volatile sbit TM1CNT_5                  @ 0x39*8+5;
extern volatile sbit TM1CNT_6                  @ 0x39*8+6;
extern volatile sbit TM1CNT_7                  @ 0x39*8+7;

//-------------------------------------------------------
//  INTF3 register bit map
//-------------------------------------------------------
extern volatile sbit I2C_STIF                  @ 0x5A*8+2;
extern volatile sbit I2C_RIF                   @ 0x5A*8+6;
extern volatile sbit I2C_TIF                   @ 0x5A*8+7;

//-------------------------------------------------------
//  INTE3 register bit map
//-------------------------------------------------------
extern volatile sbit I2C_STIE                  @ 0x5B*8+2;
extern volatile sbit I2C_RIE                   @ 0x5B*8+6;
extern volatile sbit I2C_TIE                   @ 0x5B*8+7;

//-------------------------------------------------------
//  I2CCON register bit map
//-------------------------------------------------------
extern volatile sbit I2CSTUS_0                 @ 0x68*8+0;
extern volatile sbit I2CSTUS_1                 @ 0x68*8+1;
extern volatile sbit I2CSTUS_2                 @ 0x68*8+2;
extern volatile sbit I2CSTUS_3                 @ 0x68*8+3;
extern volatile sbit ACK_EN                    @ 0x68*8+4;
extern volatile sbit CST_EN                    @ 0x68*8+5;
extern volatile sbit AWK_EN                    @ 0x68*8+6;
extern volatile sbit I2C_EN                    @ 0x68*8+7;

//-------------------------------------------------------
//  I2CDAT register bit map
//-------------------------------------------------------
extern volatile sbit I2CDAT_0                  @ 0x69*8+0;
extern volatile sbit I2CDAT_1                  @ 0x69*8+1;
extern volatile sbit I2CDAT_2                  @ 0x69*8+2;
extern volatile sbit I2CDAT_3                  @ 0x69*8+3;
extern volatile sbit I2CDAT_4                  @ 0x69*8+4;
extern volatile sbit I2CDAT_5                  @ 0x69*8+5;
extern volatile sbit I2CDAT_6                  @ 0x69*8+6;
extern volatile sbit I2CDAT_7                  @ 0x69*8+7;

//-------------------------------------------------------
//  I2CISR register bit map
//-------------------------------------------------------
extern volatile sbit TXE                       @ 0x6A*8+0;

//-------------------------------------------------------
//  ADCON register bit map
//-------------------------------------------------------
extern volatile sbit ADM_0                     @ 0x6B*8+0;
extern volatile sbit ADM_1                     @ 0x6B*8+1;
extern volatile sbit AINOUT_0                  @ 0x6B*8+4;
extern volatile sbit AINOUT_1                  @ 0x6B*8+5;
extern volatile sbit VS_LIMIT                  @ 0x6B*8+6;
extern volatile sbit VS0_OEN                   @ 0x6B*8+7;

//-------------------------------------------------------
//  WDT_TRIM register bit map
//-------------------------------------------------------
extern volatile sbit WDT_TRIM_0                @ 0x6D*8+0;
extern volatile sbit WDT_TRIM_1                @ 0x6D*8+1;
extern volatile sbit WDT_TRIM_2                @ 0x6D*8+2;
extern volatile sbit WDT_TRIM_3                @ 0x6D*8+3;
extern volatile sbit TMOD_0                    @ 0x6D*8+6;
extern volatile sbit TMOD_1                    @ 0x6D*8+7;

//-------------------------------------------------------
//  ICK_TRIM register bit map
//-------------------------------------------------------
extern volatile sbit ICK_TRIM_0                @ 0x6E*8+0;
extern volatile sbit ICK_TRIM_1                @ 0x6E*8+1;
extern volatile sbit ICK_TRIM_2                @ 0x6E*8+2;
extern volatile sbit ICK_TRIM_3                @ 0x6E*8+3;
extern volatile sbit ICK_TRIM_4                @ 0x6E*8+4;
extern volatile sbit ICK_TRIM_5                @ 0x6E*8+5;
extern volatile sbit ICK_TRIM_6                @ 0x6E*8+6;
extern volatile sbit ICK_TRIM_7                @ 0x6E*8+7;

//-------------------------------------------------------
//  VS_TRIM register bit map
//-------------------------------------------------------
extern volatile sbit VS_TRIM_0                 @ 0x6F*8+0;
extern volatile sbit VS_TRIM_1                 @ 0x6F*8+1;
extern volatile sbit VS_TRIM_2                 @ 0x6F*8+2;
extern volatile sbit VS_TRIM_3                 @ 0x6F*8+3;
extern volatile sbit LVD_TRIM_0                @ 0x6F*8+4;
extern volatile sbit LVD_TRIM_1                @ 0x6F*8+5;
extern volatile sbit LVD_TRIM_2                @ 0x6F*8+6;
extern volatile sbit SIM_RST                   @ 0x6F*8+7;

//-------------------------------------------------------
//  METCH register bit map
//-------------------------------------------------------
extern volatile sbit EVPP_EN                   @ 0x7E*8+3;
extern volatile sbit METCH_0                   @ 0x7E*8+4;
extern volatile sbit METCH_1                   @ 0x7E*8+5;
extern volatile sbit METCH_2                   @ 0x7E*8+6;
extern volatile sbit METCH_3                   @ 0x7E*8+7;

//-------------------------------------------------------
//  I2CADR register bit map
//-------------------------------------------------------
extern volatile sbit GC_EN              @ 0x7F*8+0;
extern volatile sbit I2CADR_0           @ 0x7F*8+1;
extern volatile sbit I2CADR_1           @ 0x7F*8+2;
extern volatile sbit I2CADR_2           @ 0x7F*8+3;
extern volatile sbit I2CADR_3           @ 0x7F*8+4;
extern volatile sbit I2CADR_4           @ 0x7F*8+5;
extern volatile sbit I2CADR_5           @ 0x7F*8+6;
extern volatile sbit I2CADR_6           @ 0x7F*8+7;

#endif
